1. Field of the Invention
The invention relates to an apparatus for data transmission between memories.
2. Description of the Related Art
Large amounts of data frequently have to be transmitted between volatile and non-volatile memories in microprocessor systems. The access speed is normally higher when the code of the volatile memory is used, and data is therefore normally transferred from the non-volatile memory to the volatile memory during the system start, in order to make it possible to achieve a higher running speed. Data is also transferred between volatile memory and non-volatile memory while programs are being run, in order to optimally use the restricted volatile memory and/or to ensure data protection in the event of a power failure.
The memory access is highly dependent on the type of memory used. For example, access to a volatile asynchronous RAM is relatively simple. Other memory devices, for example, non-volatile NAND flash devices, require a relatively complex access protocol. Non-volatile memory devices with an NAND structure, such as the Infineon® NROM, are currently becoming significantly more important because of the increasing memory requirement in mobile apparatuses, for example, digital photographic cameras, mobile telephones, PDAs or notebooks, and because of their extremely low costs. Random access to these memory devices is very slow and requires code and data transfer to a faster volatile memory (VM) before running the program. Owing to their internal structure, the reading or writing of relatively large data blocks, for example memory pages, is the optimum data transfer mode. For read accesses, after outputting a read command and the page address to the NAND flash device, the data is first of all transmitted to a buffer within the device, and this typically requires transmission times in the order of magnitude of several tenths of microseconds. As soon as the NAND flash device signals the completion of this transmission, all of the page data (512 or 2048 bytes) can be transmitted to the volatile memory at a high data speed of up to 40 MB per second. Furthermore, NAND flash devices have a tendency to bit errors, which necessitates bit error detection and bit error correction before data transmission to the volatile memory.
Data transfer between VM and non-volatile memory (NVM) should be carried out at the maximum possible speed in order to minimize the system start-up time. Furthermore, data transmission should be possible while the microprocessor is running programs, in order to allow dynamic loading of code and data. Furthermore, the influence of the data transfers on the performance of the microprocessor should be minimized. Ideally, the microprocessor stores a list of data transmission tasks in a volatile memory and is interrupted only after these tasks have been completely ended.
Data transmissions between memories are normally carried out using a direct memory access controller (DMAC). DMACs are, however, restricted to simple types of access and are not able to cope with more complex data transmission protocols. In the latter case, a microcontroller has to control the data transmission.
There is a need for an apparatus for transmitting data as quickly as possible between memories, and which is able to cope with even more complex data transmission protocols, but in the process requiring as little hardware as possible, and with the capability of being flexibly matched to widely differing operating conditions.